Cui, Xiaoxin

Associate Professor

Research Interests: Hardware security, 3D IC design, low-power IC design

Office Phone: 86-10-6275 7970

Email: cuixx@pku.edu.cn

Cui, Xiaoxin received the B.S. degree in cybernation from Beihang University, and the Ph.D. degree in microelectronic from Peking University, Beijing, China, in 2002 and 2007 respectively. Currently, she is an associate professor of the Institute of Microelectronic, Peking University. Dr. Cui’s current research interests include hardware security, low-power IC design, 3D IC design.

Dr. Cui has published more than 50 research papers including IEEE Transactions on Industrial Electronics (TIE), IEEE Transactions on Very Large Scale Integration Systems (TVLSI), IEEE International Symposium on Circuits and Systems (ISCAS), etc.

Dr. Cui has the research projects including NSFC, 863 project, etc. Her research achievements are summarized as follows:

1) Hardware security: The noninvasive side-channel attacks (SCAs) have been proved to be a big threat to hardware cryptosystems. She propose a low-area-time-product elliptic curve cryptography (ECC) coprocessor for GF(2m) with the ability to resist most of the existing noninvasive SCAs, which do not increase the computing time and the extra area overhead paid for the countermeasures is less than 5%. This design with the advantages of high security and low resource consumption is more competitive for the electronic portable applications, such as smart cards, RFID, etc.

2) 3D IC design: Based on the crosstalk noise problem in through silicon vias (TSVs) of 3D stacked IC, She proposed an enhanced FNS (Fibonacci number system)-based code technique to suppress the crosstalk noise in the TSV array below 6C level. The proposed technique has advantages not only on system overhead and hardware overhead, but also has low power and low bit error rate, which shows a good usability in the 3-D IC designs.

3) Low power circuit design: She focused on some advanced devices, such as FinFETs, proposed a novel device/circuit co-design scheme, which fully considered the device characteristics and more design flexibility. This new scheme firstly applied Dynamic-Adjusting Threshold Voltage Scheme (DATS) to Independent-gate (IG) mode FinFETs low-power design, and achieved the best trade-offs between leakage power and circuit performance.