Gai, Weixin

Professor

Research Interests: IC Design, transceiver, ADC

Office Phone: 86-10-6276 6952

Email: wgai@pku.eud.cn

Gai, Weixin is a professor in the Department of Microelectronics, School of EECS, and served as the vice director of Institute of Microelectronics, Peking University from 2012 to 2016. He received his B.S. and Ph.D. in electronic engineering, both from Tsinghua University in 1992 and 1997, respectively. His current research interest includes ultra high-speed transceiver for wireline communication, low-jitter all-digital phase-lock loop, energy-efficient ADC and adaptive equalization techniques.

Professor Gai has published more than 50 research papers, most of which are published in top-tier conferences and journals, such as ISSCC, JSSC, VLSI, ISCAS, and EL. He also holds 12 US patents and 8 China patents. Professor Gai has served as the committee member in the Circuit and System branch of Chinese Institute of Electronics. He is also in the Editorial Board of Journal of Electronics & Information Technology, and Journal of Electronics. He was awarded Fujitsu President award (2008), and Best Development Team by EE Times (2004). He was also the recipient of Best Paper Award at ICSICT (1995).

Professor Gai has involved in a variety of research projects including National Natural Science Foundation of China, Specialized Research Fund for the Doctoral Program of Higher Education, Huawei Innovation Research Plan, and etc. His research achievements are summarized as follows:

1) Ultra high-speed transceiver for wireline communications: To alleviate the severe channel frequency-dependent loss and power dissipation, he proposed an ultra low-power 32Gb/s transceiver based on 4-level pulse amplitude modulation. He came up with a novel pre-emphasis method by switching off the post-cursor tap when no transition happens, which greatly saves the power. He also put forward a technique automatically adjusting the threshold voltage, adaptive to the data rate, signal swing and channel loss.

2) Low-jitter all-digital phase-lock loop (ADPLL): ADPLL has the advantage of great portability and low power over its analog counterpart. In view of ring oscillator’s increasing susceptibility to supply noise as the supply keeps going down, he presented a noise-cancellation technique regulating the supply current of ring oscillator rather than its supply voltage, which achieves very high supply-noise rejection performance and digital tuning of current-regulated oscillator. For LC-tank based oscillator, he proposed a novel architecture of switched capacitor to overcome the limitation of minimum value of passive capacitor and significantly increase the resolution of frequency tuning.

3) Adaptive equalization techniques: In multi-gigabit/s chip-to-chip communication, an adaptive equalizer is often used to compensate for frequency-dependent loss such as skin effect and dielectric loss. Parameter drifting which comes with single-frequency patterns is the main problem in conventional adaptive equalizer. He figured out a pattern-balancing adaptive equalization scheme by defining several deliberately designed filter patterns (FP). Equalization gain is adjusted according to the residual level of inter-symbol interference only when FP is detected, which tremendously suppresses parameter drifting.