Feng, Jianhua
Associate Professor
Research Interests: VLST testing, hardware security
Office Phone: 86-10-6276 7302
Email: fengjh@pku.edu.cn
Feng, Jianhua is an associate professor in the Department of Microelectronics, School of EECS with the Peking University. He obtained his B. Eng. from Harbin Institute of Technology in 1986, M. Eng. from Xidian University in 1995, and Ph.D. from Xi’an Microelectronics Technology Institute in 2000 respectively. He visited Tsinghua University, China, as a Postdoctor from 2000 to 2002. His research interests include VLSI testing, design for testability, and hardware security.
Dr. Feng has published more than 40 research papers, co-authored one book, four China patents. He is a Senior Member of China Computer Federation (CCF).
Dr. Feng has more than 6 research projects including NSFC, China National Project, etc. His research achievements are summarized as follows:
1) On-chip clock jitter testing circuit design: An on-chip clock jitter testing circuit based on pulse-shrinkage TDC and accumulation register is introduced, which can be used to monitor the jitter of internal clock signal with sub-gate delay resolution. The whole testing circuit is consisted of pulse-shrinkage loop, accumulation register, XOR array, counter and control circuit. All the pulse-shrinkage units are connected in a loop to reduce the required number, so that the area can be saved and the e?ects of process variations can be reduced. Multi-cycle clock pulse measurement results are accumulated simultaneously and output in the form of serial code in monitor-mode, the clock jitter can be read directly from the serial code. The whole circuit is designed in a 65-nm CMOS process, simulation results show that the circuit can measure several GHz clock signal, with a resolution of 1 ps.
2) Test Data Compression Method: He presents a novel and efficient code, named MFDR（Modified Frequency-Directed Run-length）, for test data compression. The proposed code is a class of variable-to-variable-length prefix code. Both theoretical analysis and experimental results indicate that when the probability of 0s in the test set is greater than 0.8565, it can acquire better compression efficiency than FDR code, and compared to Hybrid Run-length code, the point is 0.8794.
3) Anti-Trojans Design Approach: Due to the stealthy nature of Trojan circuits, it’s difficult to activate Trojans to perform logic testing. An activation probability -based approach is proposed. A probability obfuscation scan chain (POSC) is presented aiming at increasing the difficulty of Trojan insertion and increasing the activation probability of the Trojan circuits. It proves to be very effective in detecting the presence of a Trojan in a circuit. This approach can effectively increase Trojan activation probability and make the detection of the Trojan more easily.
